During the so called “back end of line” (BEOL) portion of fabricating a microelectronic device, several metal layers are stacked on each other in a packaging operation. The metal wiring is separated by insulating layers comprised of dielectric material to prevent undesirable crosstalk between the metal layers. Interconnects in the form of vias and trenches are used to form electrical pathways through the dielectric material between the metal layers. As the size of a circuit shrinks to enable faster speeds for devices and a higher density to accommodate more chips per substrate and increased productivity, there is a significant challenge to manufacture vias with the appropriate size and shape to optimize device performance.
Reliability is also an increasing concern as interconnects become smaller and higher current densities are employed. There is a significant effort to manufacture devices in which failure mechanisms are substantially delayed or prevented from occurring by a judicious selection of material components and architecture. One leading cause of device failure is electromigration which is the movement of metal ions in a conductive element as a result of a current passing through it. A current typically flows from one metal line through a diffusion barrier at the bottom of a via and then through the via before reaching a second metal line. A compressive stress builds up on the upstream side of the diffusion barrier while a tensile stress increases with time on the opposite side of the barrier. There tends to be a movement of metal that leads to void formation in locations of tensile stress such as immediately downstream in the current flow from a diffusion barrier. Thus, the bottom of a conductive layer in a via hole is especially susceptible to void formation due to electromigration. A via structure for improving resistance to electromigration and a method of forming an improved via structure are needed to achieve better reliability.
Although copper is rapidly replacing aluminum in metal wiring because of its lower resistivity, Cu is more difficult to etch since its halides are not volatile and cannot be swept out of an etch chamber in the exhaust flow. As an alternative, an Al/Cu alloy may be used as a metal interconnect in situations where metal etching is practiced.
One prior art method to improve electromigration resistance is found in U.S. Pat. No. 6,080,660 where a first etch is used to form a via in a dielectric layer above a conductive line and a second etch step is used to remove a TiN layer on the metal line as well as part of the metal line. The method is useful in correcting a notch at the bottom of a misaligned via that can lead to void formation and a loss in reliability. A slanting but planar surface is produced on the metal line which enables a good interface with a subsequently deposited metal layer.
In U.S. Pat. No. 6,004,876, a low resistance interconnect with improved reliability is described and involves insertion of a Ti reaction prevention layer between a first metal layer and a TiN anti-reflective coating (ARC) on the first metal layer. The method prevents AIN from forming during deposition of TiN on an Al layer and avoids AIF formation when WF6 is used to deposit a W plug in a via above the Al conductive layer.
An imperfect diffusion barrier layer at the bottom of a via is claimed in U.S. Pat. No. 6,306,732 to control electromigration by reducing stress build up in a metal layer adjacent to a diffusion barrier layer. A limited flow of metal atoms is allowed through the bottom of the imperfect barrier to replace the metal depleted in the downstream side of the barrier.
A punch through via with a conformal barrier liner is mentioned in U.S. Pat. No. 6,522,013. A via is etched through a TiN ARC layer and into a first metal layer to give a concave bottom that has an undercut shape on the bottom corners. A TiN barrier layer is deposited in the via by a chemical vapor deposition (CVD) process that forms a conformal layer which is treated with a N2/H2 plasma to reduce resistivity. However, a specification for the concave shape at the via bottom is not taught or suggested. Furthermore, there is no flexibility to vary the shape depending upon the stress encountered in a particular device, the type of metal alloy, and other process issues.
Therefore, a via structure is needed that has a shape which can be modified to relieve stress in a particular product design and thereby improve electromigration resistance and reliability. It is desirable to have a via structure, with a flexible bottom shape that can be formed in a first metal layer or stopped on a layer above the first metal layer. The method to form the improved via structure should be well controlled so that the shape can be accurately reproduced in a manufacturing environment. Moreover, the method should be compatible with a variety of materials used as a diffusion barrier layer and metal layer to fill the via.